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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6709BR/D Product Preview MCM6709BR 64K x 4 Bit Static RAM The MCM6709BR is a 262,144 bit static random access memory organized as 65,536 words of 4 bits. Static design eliminates the need for external clocks or timing strobes. Output enable (G) is a special control feature that provides increased system flexibility and eliminates bus contention problems. The MCM6709BR meets JEDEC standards and is available in a revolutionary pinout 300 mil, 28 lead plastic surface-mount SOJ package. * * * * * * Single 5 V 10% Power Supply Fully Static -- No Clock or Timing Strobes Necessary All Inputs and Outputs are TTL Compatible Center Power and I/O Pins for Reduced Noise Three State Outputs Fast Access Times: MCM6709BR-6 = 6 ns MCM6709BR-7 = 7 ns MCM6709BR-8 = 8 ns BLOCK DIAGRAM A A A A A A A A A ROW DECODER * * * J PACKAGE 300 MIL SOJ CASE 810B-03 PIN ASSIGNMENT A A A A E DQ VCC VSS DQ W A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A A A A G DQ VSS VCC DQ A A A A NC MEMORY MATRIX 512 ROWS x 128 x 4 COLUMNS A A PIN NAMES A . . . . . . . . . . . . . . . . . . . Address Inputs W . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . Output Enable E . . . . . . . . . . . . . . . . . . . . . . Chip Enable DQ . . . . . . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . No Connection All power supply and ground pins must be connected for proper operation of the device. DQ * * * * * * COLUMN I/O INPUT DATA CONTROL COLUMN DECODER * * * DQ A E W G A A A A A A This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. REV 2 3/17/97 (c) Motorola, Inc. 1997 MOTOROLA FAST SRAM MCM6709BR 1 TRUTH TABLE (X = Don't Care) E H L L L G X H L X W X H H L Mode Not Selected Read Read Write Output High-Z High-Z Dout Din Cycle -- -- Read Cycle Write Cycle ABSOLUTE MAXIMUM RATINGS (See Note) Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 30 2.0 - 10 to + 85 0 to + 70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained. Storage Temperature -- Plastic Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V 10%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VIH Min 4.5 2.2 Typ 5.0 -- -- Max 5.5 VCC + 0.3* 0.8 Unit V V V VIL - 0.5** * VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width 2.0 ns) or I 30.0 mA. ** VIL (min) = - 0.5 V dc @ 30.0 mA; VIL (min) = - 2.0 V ac (pulse width 2.0 ns) or I 30.0 mA. DC CHARACTERISTICS Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (E = VIH, Vout = 0 to VCC) Output High Voltage (IOH = - 4.0 mA) Output Low Voltage (IOL = 8.0 mA) Symbol Ilkg(I) Ilkg(O) VOH VOL Min -- -- 2.4 -- Max 1.0 1.0 -- 0.4 Unit A A V V POWER SUPPLY CURRENTS Parameter AC Active Supply Current (Iout = 0 mA, VCC = max, f = fmax) AC Standby Current (E = VIH, VCC = max, f = fmax) CMOS Standby Current (VCC = max, f = 0 MHz, E VCC - 0.2 V, Vin VSS, or VCC - 0.2 V) Symbol ICCA ISB1 ISB2 MCM6709BR-6 215 95 20 MCM6709BR-7 205 85 20 MCM6709BR-8 195 75 20 Unit mA mA mA Notes 1, 2, 3 1, 2, 3 NOTES: 1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V). 2. All addresses transition simultaneously low (LSB) and then high (MSB). 3. Data states are all zero. MCM6709BR 2 MOTOROLA FAST SRAM CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested) Parameter Address Input Capacitance Control Pin Input Capacitance(E, G, W) Input/Output Capacitance Symbol Cin Cin CI/O Max 5 6 6 Unit pF pF pF AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V 10%, TA = 0 to + 70C, Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1a READ CYCLES 1 AND 2 (See Notes 1 and 2) MCM6709BR-6 Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Chip Enable Low to Output Active Output Enable Low to Output Active Chip Enable High to Output High-Z Symbol tAVAV tAVQV tELQV tGLQV tAXQX tELQX tGLQX tEHQZ Min 6 -- -- -- 3 3 0 -- Max -- 6 6 4 -- -- -- 3 MCM6709BR-7 Min 7 -- -- -- 3 3 0 -- Max -- 7 7 4 -- -- -- 3.5 MCM6709BR-8 Min 8 -- -- -- 3 3 0 -- Max -- 8 8 4 -- -- -- 3.5 Unit ns ns ns ns ns ns ns ns 4, 5, 6 4, 5, 6 4, 5, 6 Notes 3 Output Enable High to Output High-Z tGHQZ -- 3 -- 3.5 -- 3.5 ns 4, 5, 6 NOTES: 1. W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All read cycle timings are referenced from the last valid address to the first transitioning address. 4. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given device and from device to device. 5. Transition is measured 200 mV from steady-state voltage with load of Figure 1b. 6. This parameter is sampled and not 100% tested. TIMING LIMITS +5 V OUTPUT Z0 = 50 RL = 50 VL = 1.5 V OUTPUT 255 5 pF 480 The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. (a) (b) Figure 1. AC Test Loads MOTOROLA FAST SRAM MCM6709BR 3 READ CYCLE 1 (See Note) tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV NOTE: Device is continuously selected (E = VIL, G = VIL). DATA VALID READ CYCLE 2 (See Note) tAVAV A (ADDRESS) tELQV E (CHIP ENABLE) tELQX G (OUTPUT ENABLE) tGLQX Q (DATA OUT) tAVQV NOTE: Addresses valid prior to or coincident with E going low. tGLQV DATA VALID tGHQZ tEHQZ MCM6709BR 4 MOTOROLA FAST SRAM WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) MCM6709BR-6 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Write Low to Data High-Z Write High to Output Active Write Recovery Time Symbol tAVAV tAVWL tAVWH tWLWH tWLEH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 6 0 6 6 3 0 -- 3 0 Max -- -- -- -- -- -- 3.5 -- -- MCM6709BR-7 Min 7 0 7 7 3.5 0 -- 3 0 Max -- -- -- -- -- -- 3.5 -- -- MCM6709BR-8 Min 8 0 8 8 3.5 0 -- 3 0 Max -- -- -- -- -- -- 3.5 -- -- Unit ns ns ns ns ns ns ns ns ns 4, 5, 6 4, 5, 6 Notes 3 NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All write cycle timing is referenced from the last valid address to the first transitioning address. 4. Transition is measured 200 mV from steady state voltage with load of Figure 1b. 5. This parameter is sampled and not 100% tested. 6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device. WRITE CYCLE 1 tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tDVWH DATA VALID tWHQX tWHDX tWHAX MOTOROLA FAST SRAM MCM6709BR 5 WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) MCM6709BR-6 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Chip Enable to End of Write Data Valid to End of Write Data Hold Time Write Recovery Time Symbol tAVAV tAVEL tAVEH tELEH, tELWH tDVEH tEHDX tEHAX Min 6 0 6 5 3 0 0 Max -- -- -- -- -- -- -- MCM6709BR-7 Min 7 0 7 6 3.5 0 0 Max -- -- -- -- -- -- -- MCM6709BR-8 Min 8 0 8 7 3.5 0 0 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 4, 5 Notes 3 NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All write cycle timing is referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition. 5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition. WRITE CYCLE 2 tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL W (WRITE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX Q (DATA OUT) HIGH-Z tELWH tEHAX ORDERING INFORMATION (Order by Full Part Number) MCM 6709BR Motorola Memory Prefix Part Number X X X Shipping Method (R = Tape and Reel, Blank = Rails) Speed (6 = 6 ns, 7 = 7 ns, 8 = 8 ns) Package (J = 300 mil SOJ) Full Part Numbers -- MCM6709BRJ6 MCM6709BRJ7 MCM6709BRJ8 MCM6709BRJ6R MCM6709BRJ7R MCM6709BRJ8R MCM6709BR 6 MOTOROLA FAST SRAM 28 LEAD 300 MIL SOJ CASE 810B-03 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 3. CONTROLLING DIMENSION: INCH. 4. DIM R TO BE DETERMINED AT DATUM -T-. 5. 810B-01 AND -02 OBSOLETE, NEW STANDARD 810B-03. S MILLIMETERS MIN MAX 18.29 18.54 7.74 7.50 3.75 3.26 0.50 0.39 2.48 2.24 0.81 0.67 1.27 BSC 0.50 -- 1.14 0.89 0.64 BSC 0 10 1.14 0.76 8.64 8.38 6.86 6.60 1.01 0.77 INCHES MIN MAX 0.720 0.730 0.295 0.305 0.128 0.148 0.015 0.020 0.088 0.098 0.026 0.032 0.050 BSC 0.020 -- 0.035 0.045 0.025 BSC 0 10 0.030 0.045 0.330 0.340 0.260 0.270 0.030 0.040 F DETAIL Z 28 15 N D 24 PL 0.18 (0.007) M 1 14 TA S -AL G M H BRK 0.18 (0.007) P -BM TB S E 0.10 (0.004) C K DETAIL Z -T- SEATING PLANE R 0.25 (0.010) S S RAD TB S DIM A B C D E F G H K L M N P R S Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 INTERNET: http://motorola.com/sps MOTOROLA FAST SRAM MCM6709BR/D MCM6709BR 7 |
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